These are the preliminary datasheets, but there are no major spec changes at all to the final version. If you would like a GIF with a circuit diagram on I have that available. Here are the VVL1070 data sheets, I would have liked to be able to OCR them, but it was not possible due to the poor quality. Indeed on one or two pages I had trouble reading it. Any spelling errors are likely to be mine, but I've checked the reast fairly thouroughly (including fixing the serial data timing diagram which was a total farce.) There are a few obscure peices in the text, I have not attempted to resolve these, just typed them in. Most of the diagrams convert to ascii not too badly, apart from the circuit diagram, which I've included as a 300dpi gif(I had to redo all the text on this, it was illegible, even in some parts of the original) If you'r unsure on how to deal with UUENCODED binaries ask me, or check one of the FAQ's for the alt.binaries.pictures.* groups.
Page 0: VVL1070 Frequently Asked Questions.

Q What are the special advantages of the VVL1070?
A Great flexibility, very wide range of exposure control, very low cost in high volume (approaching 10$ for quantities of 100K units) (My note, I wish they wouldn't price low quantities so high, but they do,) (the manufacturers do not seem keen to deal direct and give larger discounts)

Q What package options exist?
A Evaluation devices are supplied in 44 pin LCC, production volumes in 44 pin Optical QFP. ( The package being ordered is the Optical QFP. (A normal QFP package with a window in the top.)

Q What is the value of the engineering Evaluation Kit?
A It is a ready-made operational platform with sensor socket, lenses and mounting, immediate acess to control signals and simple option selection. It avoids the time and cost of creating a layout and possible layout-related problems. (My note, but it costs around 1000$ and this is not a hard chip to use)

Q How do I display the output directly on a conventional monitor?
A You cannot, the VVL1070 is explicity designed for user designed capture and display circuitry.
(My note: I've got a design for a fairly simple circuit to do this, running the camera at 1/2 frame rate, thus 25fps for pal, 30fps for NTSC(?) the NSTC version would take it slightly out of specs(max frame rate 25Hz) but IMHO would work Ok. The design wouldn't be expensive, maybe #20?)

Q Does VVL1070 output CCIR or EIA
A Neither, it does not output in any standard format, see last question.

Q Can I run the VVL1070 outside the quoted 0.5 to 24 frames per second?
A Yes, but performance is not gauranteed.

Q Is VVL going to provide a 1070 module complete with support circuit?
A We do not plan one at this time, as users must in any case design their own interfaces.

Q Can I address individual pixels in the array?
Not directly, because the array is sequentially read, not random acess, but 1070 is expressly designed to ease frame grabbing. Put the data in RAM, and acess the 'virtual pixels' there.

Q Is 1070 a good choice for a low volume application?
A No. Unit cost benifits do not emerge below 1000-up purchaces, while NRE for user-designed interface circuitry gives high unit costs unless amortised over high volumes. VVL1011 is a better choice for low-volume applications. (My note, this is a CCIR output analogue camera. The support circuitry is not exactly difficult, you could get fairly good performance just hooking the camera up to a bidirectional printer port on a PC, with buffers for added protection. (only if all interrupts are disabled, and you grab to memory though.) I am designing a buffered I/O too, also to connect to the paralell port which eliminates problems with interupts.)

Q Can I display output without designing my own interface circuit?
A We are preparing a high level demonstration/evaluation kit with keyboard command and PC display. Availability fourth quarter 1994.( 1500$?)

Q Does VVL supply plastic lenses for 1070?
A Optical results with a trial lens have been acceptable, but lens must be fitted post-assembly. A family of lenses and mountings is under review. The lenses they are evaluating are from a manufacturer that was not willing to talk low volume

Page 1:


Monochrome monolithic Image sensor with analogue and Digital Outputs VVL1070


is a highly integrated CMOS image sensing device. In addition to a 160 * 160 pixel image sensor Array, it includes on-chip circuitry to drive and sense the array and to produce an output in analogue or digital format, user-selected by combination of logic levels on two inputs.

Analogue output is complete with synchronisation pulses. Digital output formats are 8-bit serial or parallel.

The output stage of the sensor contains a digitally controlled gain stage (DDAC). The DDAC circuit in conjunction with a comparator, performs Analogue to Digital conversion of the Photodiode array output when the camera is in digital mode.

VVL1070 features electronic exposure controll over a wide range, enabling the use of a single fixed-apature lens. Automatic exposure controll is enabled by combining the on-chip exposure controller with a few simple external components. Features:

Page 1/24


Chip-pin Descriptions


Data[7:0] ODT Digital sensor array output(8 bit). Also used to output the current Exposure and gain values, DATA[7] is most significant bit. AVO OA Analogue sensor output, Includes line and frame synch pulses. __ OE ID\/ Digital output (tristate) enable, Active low. DSYNCH OD DATA valid pulse and AVO sample clock. Data (analogue or digital) Valid on rising edge of DSYNCH. An additional line of reference pixels is generated to enable this data to be sampled. SYNC0 OD Frame start and synchronisation pulse. Immediately after the frame start pules, SYNC0, the current exposure and gain values are output on DATA[7:0]. Three DSYNC pulses are generated to enable the current exposure value(2bytes) and the current gain (1 byte) to be sampled. CLKI ID Clock input pad. Normal connection is an external crystal or resonator across CLKI and CLKO. Nominal frequency 12MHZ (internally divided by value dependant on SEL1 and SEL2). CLKI can also be driven by an external TTL clock. CLKO OD Clock oscillator output pad. See CLKI SEL1 ID^ Clock divisor select. See table 3 SEL2 ID^ Clock divisor select. See table 3 MODE1 ID\/ External or automatic exposure control. MODE1 = 0 selects external exposure control. MODE1 = 1 selects automatic exposure controll(see table 2) MODE2 ID\/ Parrallel or serial data format. MODE2=0 for paralel data, MODE2 = 1 for serial data. Don't care in analogue modes (see table 2) MODE3 ID\/ Digital or analogue output mode. MODE3=0 selects digital mode. MODE3=1 selects analogue mode. See table 2 for valid modes. FMT1 ID\/ Image window format select. Default setting. FMT1 = 0 and FMT2 = 0, selects 160*120 pixel output format. See figure 3 and table 1

More pin-outs

FMT2 ID\/ Image window format select. See figure 3 and table 1 SYNCI ID^ Frame synch pulse input pad. Resets pixel and line counters. Valid data is not available until one full frame after SYNCI. Active on falling edge. ECLK ID Exposure control clock. The number of pulses determines the magnitude of the change to the current exposure setting. See exposure control description. EUP ID Exposure direction control. See exposure control description. ___ RST ID System Reset. Active low. Asynchronus operation. Minimum reset pulse width is defined as two CLKI periods. Sets default exposure value. ____ RST0 OD On-chip power on and low-voltage reset generator. FAV IA Filtered analogue input signal. See automatic exposure control description. UVL IA Voltage reference which is compared with FAV and defines the upper video limit or white pixel threshold. See automatic exposure control description. Set externally. LVL IA Voltage reference which is compared with FAV and defines the lower video limit or black pixel threshold. See automatic exposure control description. Set externally. BCK IA Black level bias. Set externally. Nominally 2.5V at 25C VCL IA Sense amplifier calibration voltage. Set externally. Nominally 2.5V at 25C VRT IA Pixel reset level. Set externally. Nominally 2.5V at 25C VB1 IA Output sense output bias. Nominally 2.5V at 25C VB2 IA Analogue output voltage offset. Normally 1.4V at 25C. Can be used for temperature stabilisation of the analogue output. Requires external temperature dependant bias. USR IA Sensitivity control(voltage reference for DDAC). Set externally. Nominally 2.5V at 25C TEN ID\/ VVL test pin, No connect.

More Pin-Outs.

BSEL ID^ VVL test pin no connect. AVDD power Analogue power. AVSS power Analogue ground. DVDD power Digital power. DVSS power Digital ground. VDD1 power Digital power. VDD2 power Digital power. Key OA - Analogue output pad. IA - Analogue input pad. OD - Digital output pad. ODT - Tristate digital output pad. ID - Digital input ID\/ - Digital input with internal pull down. ID^ - Digital input with internal pull up.

Image Format

Two package variants are available, a 44 pin cavity LCC for sample quantities and an Optical Quad Flatpak for volume application. Pinout in either case is the same, shown below. (My note, the package ordered is the optical QFP) D V D D D D D D D D S V D ( ( ( ( ( ( ( ( Y S D 7 6 5 4 3 2 1 0 N S 2 ) ) ) ) ) ) ) ) C 2 6 5 4 3 2 1 44 43 42 41 40 _____________________________________ __ VSS1 7 / | 39 OE | | CLK1 8 | | 38 SEL1 | | CLK0 9 | | 37 SEL2 | ________________ | TEN 10 | | | | 36 FMT1 | | | | EUP 11 | | | | 35 FMT2 | | | | ECLK 12 | | | | 34 MODE1 ___ | | | | RST 13 | | | | 33 MODE2 ____ | | | | RST0 14 | |________________| | 32 MODE3 | | SYNC0 15 | | 31 AVDD | | VDD1 16 | | 30 USR | | SYNC1 17 |____________________________________| 29 VB2 18 19 20 21 22 23 24 25 26 27 28 D D A V V V B L U F A V V V C R B C V V A V S D S L T 1 K L L V O S D S Figure 1: Bonding Diagram.

Image Format

The image format is selected by the FMT1 and FMT2 pins (see table 1). If FMT1 and FMT2 are left floating internal pull-down resistors automatically select the 160pixel * 120 line image format. ____________________ |FMT1|FMT2|Image size| | 0 | 0 | 160*120 | | 0 | 1 | 120*160 | | 1 | 0 | 120*120 | | 1 | 1 | 160*160 | If one of the other image output formats is selected (i.e.120*160, 120*120 or 160*160) the overall frame time remains the same but the number of blank lines within a frame or the number of pixels within a line is modified. Figure 2 shows the relationship between the full (160*160) pixel image and the other output formats. <==============160=============> ________________________________ | | | | ^ | | | | | |________|_____________|________| | ^ | | | | | | | | | | | 120| | | | | | | | | | 160 | | | | | | \/|________|_____________|________| | | | | | | | | | | | |________|_____________|________| \/ <====120======> Figure 2: Image output formats. Note that frame and line times are constant for any image format. Additional blanking lines and pixels are automatically generated by the VVL1070.

Operating Modes

VVL1070 has a number of different operating modes, giving digital and analogue image data generation and automatic or external exposure control. The valid operating modes are selected Using the MODE pins (see table 2) |Mode3|Mode2|Mode1| Function | 0 | 0 | 0 | Digital mode paralell output, external exposure control, | | | | This is the default mode. | 0 | 0 | 1 | Digital mode paralell output, automatic exposure control | 0 | 1 | 0 | Digital mode serial output, external exposure control | 0 | 1 | 1 | Digital mode serial output, automatic exposure control | 1 | 0 | 0 | Analogue mode, external exposure control | 1 | 0 | 1 | Analogue mode, internal exposure control Table 2: Camera mode select. __ __ OE is used to enable or disable the digital outputs. When OE =1 the digital __ outputs are in a high impedance state. OE =0 enables the digital outputs. A pixel sample clock, DSYNC, is generated to indicate valid pixel data. This can be used to sample either the analogue or digital outputs, with pixel data valid on the rising edge of DSYNC. In analogue and paralell digital modes one DSYNC pulse is generated per valid pixel (see figures 6 and 8. In serial digital mode 8 DSYNC pulses are generated per valid pixel, one per bit (see fig 9) As well as qualifying the valid image data further DSYNCH pulses are generated to allow the current gain and exposure values to be sampled (valid results only in digital mode) and to sample an additional line of black reference pixels. If this data is not required these additional pulses should be ignored.

System Clock Gereration

VVl1070 generates a system clock when a quartz crystal or ceramic resonator circuit is connected to the CLKI and CLKO pins (see fig 3) The device can also be driven directly from an external clock source driving CLKI. | CLKI|---+--|----||----+ | | ___ | | / ### X1 | | \ ___ | Ceramic resonator or quartz crystal | | | | CLKO|---+-------||----+ | | cmos gate GND CLKI|-----<|----< clock in | External clock source. CLKO|----> clock out | Figure 3: Camera clock source. For greater flexibility the input frequency can be divided by 2, 4, 8, or 16 to provide the internal clock frequency. SEL1 and SEL2 are used to select the input clock frequency divisor (see Table 3). As an example, table 3 also gives the different frame rates that can be selected when CLKI=12Mhz, for each divisor. If SEL1 and SEL2 are left unconnected the internal pull-up and pull-down resistors select a clock divisor of 4. SEL1|SEL2|Divisor|CLKI |Internal Clock|Frame rate | | |(Mhz)| (Mhz) | F/sec) 0 | 0 | 2 | 12 | 6 | 22.7 0 | 1 | 4 | 12 | 3 |11.4 1 | 0 | 8 | 12 | 1.5 |5.7 1 | 1 | 16 | 12 | 0.75 |2.8 Table 3: Clock Division.

Frame timing.

The frame format for both digital and analogue modes is given in table 4 for VVL1070 operating in 160*160 mode. Note that if a 120 line or 120 pixel image format is selected DSYNC pulses will only be produced to qualify the selected number of lines or pixels. Sample pulses(DSYNC) Line No|Line Type|Analogue & | Serial Digital. parrallel digital | __________________________________________________________________________ 0 Blank line|3 pulses to sample gain |3*8 pulses to sample gain and |and exposure values. |exposure values. 1 Blank line| 0 | 0 2-161 Visible |160 per line | 160*8 pulses lines(160)| | 162 Blank line| 0 | 0 163 Black line| 160 | 160*8 pulses 164 Frame sync| 0 | 0 Pulses | | Table 4: Frame format. The VVL1070 frame rate depends upon: (i) The frequency of the clock input(CLKI) and (ii) the values applied to the SEL1 and SEL2 pins - see Table 3 The user can set their own values for CLKI, SEL1 and SEL2 subject to achieving a frame rate of between 0.5 and 24 frames per second. The frame rate is determined in the following way: An example is given with a clock input of 12Mhz and a clock divisor of 4 (i.e. SEL1=1, SEL2=0) 1 Determine clock input frequency(CLKI) - 12Mhz 2 Pixel period - (divisor*9) /CLKI Note that the factor 9 is internal to the VVL1070 and constant. Example Pixel period=(4*9)/12Mhz = 3uS

More Frame Timing.

3 Line period = (no of active pixels + line overhead) * pixel period The number of active pixels per line is always 160( even in 120 column format - see Image Format section for more information) The line overhead has a constant value of 18 pixel periods. Refer to figure 5 for more information) Example: Line period = (160+18)*3uS = 534 uS The frame overhead has a constant value of 5 line periods. Refer to table 4 for more information. Example: Frame period = (160*5) * 534uS = 88.1ms Frame rate = 1/period = 1/0.0881 = 11.35 frames per second.

Analogue mode.

In analogue mode the pixel data output is via the AVO pin. The valid pixels are qualified by a pulse on DSYNC and should be sampled using the rising edge. Additionally, synchronisation pulses are provided within the analogue output at the start of a frame and at the beginning of each line. The format of the analogue signal generated by the VVL1070 is shown below. Saturation .............................._.................................... Peak White ............................./.\................................... \ _ / \____________ __ \ / \_/ \________ / Black Level |/ \ / \ ..|___.....________/.................................\___....|... Blank Level/ | | | | Sync Level ......|___|..............................................|___|... Gnd ................................................................. |4P |4P |4P | 6P| 160P |^next line P ( pixel clock period) = 3uS (for CLKI = 12Mhz, SEL1=1,SEL2=0) Total line period = 160P+18P = 178P = 178*3us = 534uS Figure 4: Analogue Signal Line Format - AVO ____ |------line 164---------|-----lines 0,1-| ___/ / |----line 163--| 4P 4P 4P 4P 15P | __ ___________ __ __ __ __ _ ____\\ ____ ____/ |_| |___||___||___||___||___| |___| \\ |_| 28P 28P 28P 28P 28P Figure 5: Frame synchronisation format - AVO The pixel data should be sampled using the rising edge of the DSYNC(See Fig 6). Note that absolute times shown relate to VVL1070 operating with a clock input of 12MHZ and a clock divisor of 4 (I.E. SEL1=1,SEL2=0) _____ _____ ____________ _____ ___________ _____ \/Data \/ Not Valid \/Data \/ Not valid \/Data \ AVO _____/\_____/\____________/\_____/\___________/\_____/ \ | 0.167uS <--> < > 0.167uS Sample AVO on rising edge _ _ of DSYNC _ DSYNC | | | | | | _________| |__________________| |_________________| |___ <------3.00 uS-------> Figure 6: sampling AVO using DSYNC.

Digital Mode.

Paralell mode. Figure 7 shows the waveforms for the VVL1070 operating in digital mode. The 8 bit digitised pixel data is output on pins DATA[7:0] in parallel mode or DATA[0] in serial mode. The start of frame is indicated by pulse on SYNC0. The three DSYNC pulses to allow the gain and exposure values to be sampled are generated immediately after the frame start pulse. Start of frame. _ | | SYNC0 _| |___\/_____________________________________________________ /\ 160 pixel 160 pixel 160 pixel 3 pulses sample pulses sample pulses sample pulses DSYNC ____|||_\/___|||||||||||||||_____|||||||||||||||___|||||||||||| /\ 2 blank lines ________\/_________________________________________________________ DATA[7:0] ||| /\ | | | | | ________\/_______________________________________________________ ^ /\ Line 2 Line 3 Line 4 current gain and exposure values End of frame. _ | | SYNC0 _________________________________________________________| |___ 160 pixel sample pulses DSYNC _________|||||||||||||||_______________________________________|||___ ___________________________________________________________________ DATA[7:0] | | | ||| _________________________________________________________________ Line 162 Line 163 Line 164 Line 0 (blank line) (Black line) (Blank line) Figure 7: 160*160 Frame timing (Digital modes) The pixel data should be sampled using the rising edge of DSYNC (See fig 9) _ _ DSYNC __________| |_________________________| |__________________ _______ _____ ___________________ _____ _________________ DATA[7:0]XXXXXXX\/ 1 \/XXXXXXXXXXXXXXXXXX \/ 2 \/XXXXXXXXXXXXXXXXX _______/\_____/\___________________/\_____/\_________________ Pixel 1 Pixel 2 Figure 8: Paralell data output.

Serial mode

In serial output mode the 8-bit data is output on the DATA[0] most significant bit first. Additional DSYNC pulses are generated to allow each bit to be sampled. Data is sampled on rising edge of DSYNC. DSYNC _ _ _ _ _ _ _ _ _ _ _ _ _ __| |__| |__| |__| |__| |__| |__| |__| |_______| |__| |__| |__| |__| | ___ ___ ___ ___ ___ ___ ___ ________ ___ ___ ___ ___ ___ / 7 \/ 6 \/ 5 \/ 4 \/ 3 \/ 2 \/ 1 \/0 \/ 7 \/ 6 \/5 \/ 4 \/ 3 \ \___/\___/\___/\___/\___/\___/\___/\________/\___/\___/\___/\___/\___/ DATA[0]

Exposure and Gain Control

Exposure control VVL1070 has two exposure control modes, mode 0 giving external digital control, Mode 1 automatic exposure control. External Exposure Control The exposure value is a 16 bit number which can be incremented or decremented in predefined steps to change the integration period. Two inputs control these changes, ECLK (exposure clock) and EUP (Exposure direction control). The exposure value can be modified at any time during a frame except during the frame start pulse (SYNCO) which is the time when the new exposure value is latched through to the camera control sequencer. Each ECLK pulse changes the exposure value by 6.25%. EUP controls the direction of change, high to increase exposure, low to decrease. Note that the new value is not effective until the following frame. The frequency of ECLK should be less than or equal to CLKI but it need not be synchronus. There is no other limit to the number of ECLK pulses which may be applied within a single frame. The integration period is a multiple of the pixel clock and is defined by the following formula: FI is a number of image line periods defined by the most significant 8 bits of the 16 bit number. RST is a number of pixel periods defined by the least significant 8 bits. RST and FI are auromatically constrained within predifined limits. See Table 5 below. |Label|Minimum|Maximum| | FI | 0 | 162 | | RST | 16 | 167 | Table 5: exposure value limits. if FI > 8 then RST is clamped to it's maximum value 167.

Exposure and Gain Control

Note That: a) On power up or reset, VVL1070 will default to it's maximum exposure value. b) 131 ECLK pulses are required to change exposure from maximum to minimum. Further pulses will have no effect on exposure. c) b) 131 ECLK pulses are required to change exposure from minimum to maximum. Further pulses will have no effect on exposure, but if the sensor is operating in analogue mode, gain will be increased. See "Gain control, Analogue mode" below. d) In moving from minimum exposure to maximum, the specific count values of 54 and 77 ECLK pulses should be avoided as these may give spurious exposure effects. Exposure range For each values of pixel clock period, VVL1070 has an exposure range of 1800:1 The user can extend the range by choosing a different clock divisor (see Table 3) or by using a different clock frequency. Automatic Exposure Control In Mode = 1, VVL1070 will automatically control exposure with the aid of a few external components. These provide reference voltages on UVL and LVL, and a video integrating filter capacitor filter on FAV. See support schematic Figure 17 and component list Table 10 Note that by reducing the value of the video integrating capacitor, the exposure control can be biased towards the lower portion of the image which can be usefull in backlit conditions.
Analogue Mode In analogue output mode, the gain of the output stage can be modified to extend dynamic range once maximum exposure has been reached, using a digitally controlled gain stage initially set (default condition) to it's minimum gain value of unity. Once maximum exposure value has been reached, the 8-bit gain control value can be integrated or decremented using ECLK and EUP. Unlike the exposure counter (6.5% change per ECLK pulse), gain control value is modified by one count per ECLK pulse. Maximum control value is 247(reached after 247 ECLK pulses), Which equates to a gain of approximately 32. The relationship between actual gain and is approximately an inverse law.) Further ECLK pulses will be ignored. Digital mode In Digital mode, the above gain control arrangement is not available. Instead gain may be controlled by varying the bias voltage on USR as in the following table: |USR | Gain | Comment | |3.00V| 0.67 |Minimum gain | |2.00V| 1.00 |Normal operating point for USR | |1.00V| 2.00 |Max gain over functional frequency and | | | |temperature range. | |0.50V| 4.00 |With values of USR less than 1.00V, conversion | | | |accuracy is not gauranteed over full operating | |0.25V| 8.00 |range | Table 6: Digital Mode Sensitivity Control.

Timing and Output Signals for Exposure and Gain Values

Timing and Output Signals for Exposure and Gain Values In both analogue and digital modes, the current exposure and gain values are output once per frame immediately after SYNCO. Three bytes, two for exposure and one for gain are output on DATA[7:0] and can be sampled by DSYNC. figure 10 shows data format for exposure and gain values and shows exposure or gain values being increased by five steps. (CLKI pulses are not shown to scale, ECLK must be slower than CLKI) CLKI |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| _____________ SYNCO ____| |_______________________________________________ ________________________ EUP _________________________________________| {increment exposure} {by 5 steps.} _ _ _ _ _ ECLK _____________________________________________| |_| |_| |_| |_| |___ _ _ _ DSYNC ________________________________| |_| |_| |________________________ # ____________________________________________________________________ DATA[7:0] |1| |2| |3| ____________________________________________________________________ Byte 1 and 2 are current exposure value, 3 is current gain value. Figure 10: Exposure control timing. In digital mode the digitally controlled gain stage forms part of a successive approximation A/D converter and therefore cannot be used to modify gain. In both digital and analogue the current exposure and gain values are output by the chip once per frame immediately after the SYNCO (see fig 11). Three bytes (two for exposure and one for gain) are output on DATA[7:0] and can be sampled by DSYNC. The data format for the exposure control values are shown in figure 11. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ |0|1|2|3|4|5|6|7| |0|1|2|3|4|5|6|7| |0|1|2|3|4|5|6|7| |_|_|_|_|_|_|_|_| |_|_|_|_|_|_|_|_| |_|_|_|_|_|_|_|_| {------Exposure--------------------} {-----Gain------} Figure 11: Exposure and Gain Value Output Format Note that in digital mode the gain value is not valid since there is no gain control.

Maximum and Minimum Ratings

Item Symbol Rating | Unit _______________________________________|______|_________________|________________ Supply voltage w.r.t. GND | VDD | -0.5 to +6.0 | V Input voltage w.r.t. GND | |-0.5 to VDD+0.5 | V Free air operating temperature range. | | -40 to +85 | C Free air functional temperature range. | | -20 to +50 | C Storage temperature | | -40 to +120 | C Relative Humidity | | 95 | % (non-condensing at 37C) | | | Maximum power dissapation | | 280 | mW (25C and 23 f.p.s.) | | | Junction temperature | | 150 | C ESD protection (tested to Mil Spec | | 2000 | V 883C, notice 7, method 3015.6) | | | Input Current | | +-20 | mA Optical power density | | 100 | mW/cm^2 Soldering temperature and time | | 260,10 | C,sec Minimum clock frequency (external) | | 0.26 | Mhz (internal) | | 0.13 | Mhz Maximum clock frequency (external) | | 48.63 | Mhz (internal) | | 6.07 | Mhz Table 7: Absolute maximum ratings.

Recommended Voltages.

Input|Unit |Min | Typical| Max| VDD | V |4.75 | 5.00 |5.25| VRT | V |2.49 | 2.50 |2.51| VCL | V |2.49 | 2.50 |2.51| BCK | V |2.49 | 2.50 |2.51| USR | V |1.00 | 2.00 |3.00| CLKI | V(p-p) |4.75 | 5.00 |5.25| Table 8: Operating Conditions The input voltages given in table 8 are the supply and bias voltages required for correct operation of the image sensor. Input and Output Pad DC Charachteristics Parameters |Symbol|Minimum|Maximum|Unit|Conditions Power Supply | VDD | 4.75 | 5.25 | V | Digital inputs | VIL | -0.5 |0.3*VDD| V | (CMOS) | VIH |0.7*VDD|VDD+0.5| V | Digital outputs | VOL | | 0.4 | V | IOL=2mA (CMOS) | VOH |VDD-0.5| | V | IOH=100uA | | 2.4 | | V | IOH=2mA Specified at Ta=25C | | | | | Table 9: DC parameters at pads.

I/O pad Capacitance and Impedance

I/O pad Capacitance and Impedance |Capacitance|Impedance| Pad Name | (pF) | (Kohm) | ___ | Min |Max | Min|Max | RST, ECLK, EUP, | | 8 | |500 | Input leakage current +-10uA KLKRC, FAV, | | | | | UVL, LVL, USR | | | | | | | | | | SEL1,SYNCI | | 8 | 30 |500 | Internal pull-up resistance __ | | | | | 35Kohm to 150Kohm SEL2, OE, MODE1, | | 8 | 33 |115 | Internal pull-down resistance MODE2, MODE3, | | | | | 35Kohm to 150Kohm FMT1,FMT2, | | | | | TEN, IBC, BSEL | | | | | ____ | | | | | RSTO, DSYNC, | | 8 | 1.2|2.5 | Output current 2mA (max) SYNCO | | | | | | | | | | DATA[7:0] | | 8 | 1.2|500 | 3-state output leakage current +-10uA | | | | | Output current 2mA (max) BCK | | 10 | |500 | | | | | | VCL | 10 | 250 | 4 | 500| | | | | | VRT | 10 | 950 | 1 | 500| | | | | | CLKI | | 10 | | | | | | | | CLKO | | 10 | | | | | | | | KLK | | 8 | 0.6|1.25| Output current 4mA (max) | | | | | AVO | | 8 | 1.3|6.5 | Output current 0.5mA (max) | | | | | AVDD, AVSS | | | | | | | | | | DVDD, DVSS | | | |1.7 | Unloaded outputs. | | | | | VDD1, VDD2, | | | |1.7 | Unloaded outputs. VSS1,VSS2 | | | | | Table 10: I/O pad Capacitance and Inductance.

Electrical and Optical Parameters

Measure |Conditions|Units |Min |Typical |Max | | | | | IDD | | mA |5.6 |6.0 |6.4 | | | | | IDA | | mA |9.5 |10.0 |10.5 | | | | | Saturation | | V |2.80 |2.90 |3.00 | | | | | Peak White | | V |2.70 |2.80 |2.90 | | | | | Black Level | | V |1.05 |1.20 |1.35 | | | | | Dark current (*1) | |times sat. |0.00039|0.00040 |0.00041 | | | | | Fixed-pattern Noise | |(rms) mV | | |80 | | | | | Random Noise | |(rms) mV | | |20 | | | | | Sensitivity (*2) | USR=3.00V|uW/cm^2 | |20 | | | | | | Clock Breakthrough | |(p-p) mV | | |100 | | | | | Blooming Tolerance (*3) | |times sat. | 40 | 60 | General test conditions. Analogue output characteristics measured on AVO w.r.t. GND (0V) Ta=25C VDD=5.00V (AVDD, DVDD, VDD1, VDD2) DND=0.00V (AVSS, DVSS, VSS1, VSS2) VRT=2.50V VCL=2.50V USR=2.50V VB1=2.50V VB2=1.40V External clock input utilising CLKI, 12Mhz, 50% duty cycle. Internal frequency divisor set to 4 (default) i.e. SEL2=0, SEL1=1 Image output format 160 * 120 pixels (landscape default) i.e. MODE2=0, MODE1=0 Exposure value set to maximum (default) Gain set to default value. Digital outputs not connected. (DATA[7:0], SYNCO, DSYNC) *1 Contribution as a multiple of saturation, at 25C, 20ms integration period *2 Energy required to saturate sensor output. Illumination - Tungsten-halogen, colour temp. 3000K. Irradiance measured 300- 1100nm *3 Overexposure factor causing contribution of 15% of saturation at a diode 15 pixels vertically from the center of a bright spot of diameter 10 pixels. At max exposure and 12Mhz ext. clock. Temp=25C Table 11: Performance Characteristics.

Page 22 is a UUENCODED 300dpi GIF sent seperately.

Component values for above Circuit.

Component Part No/Value Type IC1 |ASIS-1070 |(44 LCC SKT) REG1 |LM78L05ACM |5V regulator R1 |22Kohm |0805, 2% R2 |2Kohm |0805, 2% R3 |27Kohm |0805, 2% R7, R8, R12, R20, R21, R22 |10Kohm |0805, 2% R9, R10 |1Kohm |0805, 2% R11 |27Kohm |0805, 2% R13 |1Mohm |0805, 2% R14 |120ohm |0805, 2% R15 |270ohm |0805, 2% R16 |100Kohm |0805, 2% R17 |470ohm |0805, 2% R18, R19 |1Kohm |0805, 2% C1, C2, C3 |0.1uF |ceramic C4 |10uF |6V tantalum C5, C6 |0.2uF |ceramic C7 |1nF |COG C8, C9, C11, C12, C18, C19 |0.1uF |COG C13, C14 |33pF |COG C15 |220pF |COG C16 |10nF |COG C17 |22nF |COG X1 |12Mhz |Crystal or ceramic resonator | | T1 |BC849C |SOT-23 F1-F5 |TBAF |SOT filters CON |18 way connector|SOT Table 12: Recommended circuit Components.

Normalised spectral response

(nm) response 300 0 350 0.15 400 0.45 450 0.6 500 0.75 550 0.88 600 0.9 650 0.95 700 0.85 750 0.90 800 0.7 850 0.42 900 0.35 950 0.35 1000 0.1 1050 0.03 1100 0.01 Approximate graph, real graph is a little smoother. 1 --------------------------/\_-------------------------------- | | | || | | | | /| | || /\ | | 0.9----------------------/-|/---|----/-\------------------------ | | /\_/ || / \ | | | |_/ || / \ | | 0.8---------------/-------------/\/----\------------------------ | || | \_/\ | | | || | | | | 0.7--------------|--------------------------|------------------- | \/ | | | | | | | | | | | | 0.6----------\/-----------------------------|------------------- | | | | | | | | | | | | | | 0.5----------|------------------------------|------------------- | | | | \ | | | |\/ | | | | | 0.4-------|-----------------------------------\___-------------- | | | | | \ | | | | | | \/\_ | 0.3------|---------------------------------------------\-------- | | | | | \ | | | | | | \ | 0.2-----|------------------------------------------------\------ | | | | | \ | | | | | | \___| 0.1-----|------------------------------------------------------- | | | | | | | | | | | | 0.0*--/--------------------------------------------------------- 300 500 700 900 1100 Figure 13: Normalised Spectral response. End Of Datasheet. Return to homepage.